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The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits by Paul Jespers
The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits by Paul Jespers
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The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits

The semi-empirical and compact model approaches
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Description

In "The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits", we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com  allow redoing the tests.
Release date Australia
May 3rd, 2012
Author
Audience
  • Professional & Vocational
Illustrations
XVI, 171 p.
Pages
171
Dimensions
156x234x10
ISBN-13
9781461425052
Product ID
20334736

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