Verification Plans

The task of verification is always larger than the task of the design effort. Why? Because the verification system has to encompass the entire functionality of the device under verification. It has to mimic the real world environment that the device will actual operate in. It needs to catch functional errors. It needs to give feedback information to guide further verification. The design effort proceeds from a design specification. Verification systems need to proceed from a verification plan. A comprehensive document that describes the verification system and all its components. A plan that details how the verification system will be built. With the advent of hardware verification languages, today’s verifications systems have grown in complexity making verification plans even more paramount. This work is a practical guide on how to get a verification team jumpstarted into verification success by the joint creation of a verification plan.
The book includes: a detailed five day approach that gives day-by-day, step-by-step instructions on how to design and document your verification system; an introduction to hardware verification languages, their pseudo-random mindset, their enabling methodologies (generation, checking and coverage), and how these effect the development of a verification plan; practical guidance in common people issues, formatting decisions and information extraction methods to enhance your verification plan brainstorming sessions; and an appendix full of verification plan examples and support documents.