Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Name: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
SKU: 21608706
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Description

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Author Biography:

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.

Release date Australia

December 2nd, 2013

Author

Audience

Professional & Vocational

Illustrations

115 Illustrations, color; 18 Illustrations, black and white; XVIII, 245 p. 133 illus., 115 illus. in color.

Pages

245

Dimensions

155x235x20

ISBN-13

9783319023779

Product ID

21608706

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