Non-Fiction Books:

Digital System Verification

A Combined Formal Methods and Simulation Framework

Customer rating

Click to share your rating 0 ratings (0.0/5.0 average) Thanks for your vote!

Share this product

Digital System Verification by Lun Li
36% off
$63.99 was $99.99
or 4 payments of $16.00 with Learn more
In stock with supplier

The item is brand new and in-stock in with one of our preferred suppliers. The item will ship from the Mighty Ape warehouse within the timeframe shown below.

Usually ships within 2-3 weeks


Delivering to:

Estimated arrival:

  • Around 16-22 November using Express Delivery
    Mighty Ape can deliver this product within 1-2 business days (usually overnight) to urban centres across Australia, and some remote areas. Learn more
  • Around 19-26 November using standard courier delivery


Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative. This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation.
Release date Australia
January 1st, 2010
Country of Publication
United States
Morgan & Claypool Publishers
Product ID

Customer reviews

Nobody has reviewed this product yet. You could be the first!

Write a Review

Marketplace listings

There are no Marketplace listings available for this product currently.
Already own it? Create a free listing and pay just 9% commission when it sells!

Sell Yours Here

Help & options

  • If you think we've made a mistake or omitted details, please send us your feedback. Send Feedback
  • If you have a question or problem with this product, visit our Help section. Get Help
  • Seen a lower price for this product elsewhere? We'll do our best to beat it. Request a better price
Filed under...