Fast, Efficient and Predictable Memory Accesses

Name: Fast, Efficient and Predictable Memory Accesses
SKU: 11092023
Price: 260.99 AUD
Availability: InStock

Optimization Algorithms for Memory Architecture Aware Compilation

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Paperback / softback

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Description

Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

Author Biography:

Prof. Peter Marwedel is well established within the Electronic Design Automation community, he has co-authored four books with us and also published his best-selling Embedded Systems Design (text)book with Springer.

Release date Australia

October 19th, 2010

Author

Audience

Professional & Vocational

Edition

Softcover reprint of hardcover 1st ed. 2006

Illustrations

XII, 258 p.

Pages

258

Dimensions

156x234x14

ISBN-13

9789048172009

Product ID

11092023

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