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Layout Optimization in VLSI Design

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Description

The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout optimization problems emerging with the advent of very deep submicron technologies in semiconductor processing. Audience: A reference work for graduate students, senior undergraduates, and researchers.
Release date Australia
November 23rd, 2010
Audience
  • Professional & Vocational
Contributors
  • Edited by Bing Lu
  • Edited by Ding-Zhu Du
  • Edited by S. Sapatnekar
Illustrations
VIII, 288 p.
Pages
288
Dimensions
155x235x16
ISBN-13
9781441952066
Product ID
8941537

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